Static Timing Analysis

Project : ConnectFour
Build Time : 05/13/14 16:14:38
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
UART_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 40.259 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 51.419 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 51.419 MHz 19.448 22.219
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.356
macrocell10 U(3,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell1 U(3,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 79.828 MHz 12.527 29.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 6.332
macrocell12 U(3,2) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 80.199 MHz 12.469 29.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 6.274
macrocell11 U(3,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 80.308 MHz 12.452 29.215
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 6.257
macrocell4 U(3,1) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 80.308 MHz 12.452 29.215
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 6.257
macrocell8 U(3,1) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 86.573 MHz 11.551 30.116
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 5.356
macrocell3 U(3,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 86.573 MHz 11.551 30.116
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.356
macrocell15 U(3,0) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 40.259 MHz 24.839 13016.828
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(2,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 5.814
macrocell2 U(2,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.905
datapathcell3 U(2,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 40.720 MHz 24.558 13017.109
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_2 5.533
macrocell2 U(2,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.905
datapathcell3 U(2,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 41.501 MHz 24.096 13017.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,0) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 5.071
macrocell2 U(2,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.905
datapathcell3 U(2,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 44.815 MHz 22.314 13019.353
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART:BUART:tx_bitclk_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART:BUART:tx_bitclk_enable_pre\/main_0 3.366
macrocell19 U(2,2) 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:tx_bitclk_enable_pre\/main_0 \UART:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:tx_bitclk_enable_pre\/q \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 3.628
datapathcell2 U(2,0) 1 \UART:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART:BUART:tx_bitclk\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.972 MHz 22.236 13019.431
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,1) 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/clock_0 \UART:BUART:tx_bitclk\/q 1.250
Route 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/q \UART:BUART:counter_load_not\/main_3 3.211
macrocell2 U(2,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.905
datapathcell3 U(2,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 51.427 MHz 19.445 13022.222
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 6.788
macrocell10 U(3,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell1 U(3,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 53.648 MHz 18.640 13023.027
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.882
macrocell16 U(3,2) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 5.558
statusicell1 U(3,2) 1 \UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 57.205 MHz 17.481 13024.186
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,2) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 5.796
macrocell7 U(3,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.865
count7cell U(3,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 58.841 MHz 16.995 13024.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_2 4.536
macrocell23 U(2,0) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_2 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.259
statusicell2 U(2,0) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:rx_address_detected\/q \UART:BUART:sRX:RxBitCounter\/load 58.952 MHz 16.963 13024.704
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,2) 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/clock_0 \UART:BUART:rx_address_detected\/q 1.250
Route 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/q \UART:BUART:rx_counter_load\/main_0 5.278
macrocell7 U(3,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.865
count7cell U(3,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 8.041
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 5.356
macrocell3 U(3,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 8.041
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.356
macrocell15 U(3,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 8.942
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 6.257
macrocell4 U(3,1) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 8.942
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 6.257
macrocell8 U(3,1) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 8.959
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 6.274
macrocell11 U(3,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 9.017
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 6.332
macrocell12 U(3,2) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 14.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.685
Route 1 Net_30 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.356
macrocell10 U(3,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell1 U(3,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_state_3\/q \UART:BUART:rx_load_fifo\/main_3 3.835
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,2) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_load_fifo\/main_3 2.585
macrocell9 U(3,2) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_3 3.835
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,2) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_3 2.585
macrocell12 U(3,2) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_3\/main_3 3.839
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,2) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
macrocell13 U(3,2) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_3\/main_3 2.589
macrocell13 U(3,2) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_address_detected\/q \UART:BUART:rx_load_fifo\/main_0 3.862
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,2) 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/clock_0 \UART:BUART:rx_address_detected\/q 1.250
Route 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/q \UART:BUART:rx_load_fifo\/main_0 2.612
macrocell9 U(3,2) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_address_detected\/q \UART:BUART:rx_state_2\/main_0 3.862
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,2) 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/clock_0 \UART:BUART:rx_address_detected\/q 1.250
Route 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/q \UART:BUART:rx_state_2\/main_0 2.612
macrocell12 U(3,2) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_address_detected\/q \UART:BUART:rx_state_3\/main_0 3.864
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,2) 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/clock_0 \UART:BUART:rx_address_detected\/q 1.250
Route 1 \UART:BUART:rx_address_detected\ \UART:BUART:rx_address_detected\/q \UART:BUART:rx_state_3\/main_0 2.614
macrocell13 U(3,2) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 4.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,2) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell25 U(2,2) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.782
macrocell25 U(2,2) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:rx_state_0\/main_8 4.044
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_state_0\/main_8 2.794
macrocell11 U(3,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:pollcount_1\/main_2 4.056
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
macrocell4 U(3,1) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:pollcount_1\/main_2 2.806
macrocell4 U(3,1) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:tx_state_1\/main_2 4.078
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:tx_state_1\/main_2 2.828
macrocell21 U(3,0) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 29.647
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,2) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_25/main_0 2.799
macrocell1 U(3,2) 1 Net_25 Net_25/main_0 Net_25/q 3.350
Route 1 Net_25 Net_25/q Tx_1(0)/pin_input 7.269
iocell2 P3[1] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 14.979
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000